发明名称 PROCESS AND INSTALLATION FOR DETERMINING THE THICKNESS OF LAYERS IN LAYERED SEMI-CONDUCTORS
摘要 <p>In the process described, a sample of a layered semi-conductor (4) is placed in contact with an electrolyte (2) then subjected to anodic etching during which the depth of etching is determined by integration of the current. During etching, the sample (4) is also excited by an electric signal and the real component of the admittance and hence the conductance of the probe at the frequency of excitation is determined, the extreme values of this component are analysed, and the values of the depth of etching corresponding to these extremes, which characterize the junctions between the layers of the sample (4) tested, are determined. The installation for implementing the procedure contains a cell (1) filled with electrolyte (2) in which is immersed a graphite electrode (5), a saturated calomel electrode (6), and a platinum electrode (7) surrounding the surface of the sample (4) subjected to etching, electrodes (8, 9) neither of which touch the surface of the sample (4) subjected to etching, a potentiostat (13) which is connected to the calomel electrode (6) and the direct current source (12), the current integrator (14), which receives the etching current intensity signal, a generator (15) which emits a periodic signal between the sample (14) and the metal electrode, and the measurement element (16) for measuring the conductance of the sample (4).</p>
申请公布号 WO1988009053(A1) 申请公布日期 1988.11.17
申请号 HU1988000030 申请日期 1988.05.04
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