| 摘要 |
PURPOSE:To prevent the slowdown of a signal transfer rate without inducing a punch through by a method wherein the formation of the source and drain regions of an N-ch transistor and a high-resistance element is finished up before the formation of a P-ch transistor. CONSTITUTION:A heat treatment, which a P<+> boron diffused layer 15 of source and drain regions of a P-ch transistor is subjected to, not only is avoided to the utmost, but this structure is constituted into an offset structure in advance using the sidewalls, which consist of a first interlayer insulating film 10, of the sidewalls of gate poly Si electrodes 7(a)-7(c) as masks in an ion- implantation of boron and a heat treatment subsequent to that is utilized to attain a matching property. Thereby, such problems as an increase in a punch- through in the P-ch transistor and the slowdown of a response speed due to the augmentation of an overlapping capacity can be avoided. |
