| 摘要 |
PURPOSE:To contrive improvement in a gate delay time or cut-off frequency characteristics, by a method wherein, using a film containing required impurities as a source of impurities and a mask for lift-off, base series resistance is reduced by self-alignment of an emitter electrode, emitter region and base impurity diffusion region. CONSTITUTION:A P<+>-type impurity diffusion region is formed by diffusing the Zn added to a silicon oxide film 11 into a semiconductor substrate in the depth reaching a P<+>-type GaAs base layer 4 by conducting a heat treatment, and as a result, an emitter region 5E is marked out. A resist mask 13, with which the part outside the P<+>-type impurity diffusion region 7 will be coated, is provided from the middle part of the silicon film 11, and gold and the like is vapor-deposited as an emitter electrode layer. Among the above-mentioned substance, the part 10b deposited on the resist mark 13 is lifted off by exfoliation and removal of the mask 13, the part 10a deposited on the silicon oxide film 11 is lifted off by removing the film 11, and an emitter region 10 is patterned. As the emitter electrode 10, the emitter region 5E and the P<+>-type impurity diffusion base contact region 7 are self-aligned, base series resistance can be brought to a minimum.
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