| 摘要 |
PURPOSE:To increase the remainder multiplication processing by processing a multiplier by every bits, whose number is larger than two, in accordance with a high-order Booth algorithm to reduce the number of loops and performing the processing in the loop in the time corresponding to addition in one stage. CONSTITUTION:Initially, an integer (a) is stored in first and second registers 201 and 208 and an integer (b) is stored in a shift register 209, and a storage part simultaneously outputs product qXn and product (q+2)Xn with a bit pattern in digits, whose number is equal to or larger than the number of digits of an integer (n) of the output of a left shifter 202, as the address. A first subtractor 204 subtracts the first output qXn of the storage part from the output of the left shifter and outputs the result to the first register. A second subtractor subtracts the second output (q+2)Xn of the storage part and outputs the result to the first register. First and second subtractors and first and second operating parts are simultaneously operated completely synchronously, and this processing is repeated.
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