| 摘要 |
PURPOSE:To process data at high speed with little memory capacity by shifting next one bit data to a shift register, repeatedly retrieving a data table until run length data is detected with the aid of a judgement means and obtaining desired data from the primary or the secondary decoding table when the data is control data. CONSTITUTION:The data outputted one by one bit from a reception buffer 1 is received by the shift register 2 and set in a initial state. The zero value of a bit transferred to the register 2 is counted by a zero counter 3 and added to the secondary decoding table 5 as an address through a buffer register 6 controlled by a control circuit 8. Then the output of the register 2 is added to the primary decoding table 4 as an address. The bit of the decoding data of each table 4 and 5 is judged by the judgement circuit 7, and the circuit 8 is controlled based on the result of the judgement. Then the desired data is outputted at high speed by repeatedly retrieving the tables 4 and 5 with the aid of the circuit 7 until the run length data is detected.
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