发明名称 PARITY DETECTING CIRCUIT
摘要 PURPOSE:To easily obtain the parity detecting result with a small circuit scale by using an exclusive OR circuit which applies the serial data input and the output of a temporary memory circuit as inputs and a temporary memory circuit which applies the output of the exclusive OR circuit as an input. CONSTITUTION:An exclusive OR circuit 102 calculates the initial value 0 of the output 105 of a latch 103 as well as the latched data. Then the output 1 of the circuit 102 is temporarily stored in the latch 103 by a clock obtained by inverting the clock input. When the output 105 of the latch 103 is stabilized to '1', two pieces of inputs 104 and 105 of the circuit 10 are set to '1'. Thus the output of the circuit 102 is changed to '0'. Then a 2nd bit 0 of a serial data input 100 is latched by a 1st bit of a shift register 101. Thus the output 104 is changed to '0', therefore the output of the circuit 102 is changed again to '1' to be stored temporarily in the latch 103. Hereafter, the exclusive OR arithmetic operations are carried out in the same way. Then the data stored temporarily by the latch 103 can be obtained at the 9th clock as the parity checking result.
申请公布号 JPS63197240(A) 申请公布日期 1988.08.16
申请号 JP19870030359 申请日期 1987.02.12
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 SASANUMA HIROSHI
分类号 G06F11/10 主分类号 G06F11/10
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