| 摘要 |
PURPOSE:To expand an alignment margin when a gate electrode is formed and to implement miniaturization, by etching an impurity diffused layer other than a gate channel part and the exposed part of a part of a semiconductor substrate, and forming another impurity diffused layer by self-alignment. CONSTITUTION:Polysilicon 5 is formed on a gate oxide film 4. The polysilicon 5 and the oxide film 4 are patterned after the pattern of a resist mask 6. An n-type diffused layer 3 is etched in a silicon substrate 1 with the resist 6 as a mask. Then, a resist mask 7 is formed, and As<+> ions are implanted. An n-type diffusion layer 8 for controlling a gate threshold voltage is formed. A gate oxide film 9 is further formed. Polysilicon 10 is formed on the film 9. Then, the polysilicon electrode of a gate is formed by patterning and etching. |
