发明名称 HIERARCHY MEMORY CONTROL SYSTEM
摘要 PURPOSE:To avoid such a case where a serious trouble such as a system stop, etc., caused by a trouble of a change array, by providing a mode to always rewrite data back to a main memory in a replacement mode for a hierarchy memory device of a store-in system. CONSTITUTION:In case the troubles of change arrays 130 and 140 are detected while two rows are working separately from each other due to occurrence of a trouble, a separating request is delivered from a trouble processing part. In this case, a line-back mode register 152 is set if a buffer memory is separated in the most reduced state. Thus the change bit value is always kept at '1' in terms of the reading results of both arrays 130 and 140. Then a line-back request register 167 is always set in a replacement mode of buffer memories. Therefore the data on a main memory are never broken down although the troubles of both arrays 130 and 140 are detected since the line-back operation is always carried out.
申请公布号 JPS62285154(A) 申请公布日期 1987.12.11
申请号 JP19860127885 申请日期 1986.06.04
申请人 HITACHI LTD 发明人 TAGAMI MASAHIKO;NAKAMURA KOJI
分类号 G06F12/08 主分类号 G06F12/08
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