| 摘要 |
PURPOSE:To read out the desired data at high speed by omitting the retrieval of an address conversion index buffer TLB in an indirect addressing mode and giving addresses to a buffer memory address array BAA and a buffer storage BS. CONSTITUTION:In an indirect addressing mode the latter half 4B (line 700) of a data register 650 is used as the 2nd logic address. The bits 0-19 and 20-32 of the line 700 are separated to the lines 710 and 720 respectively. At the 2nd access of the indirect addressing mode, the retrieval of a TLB is omitted and a comparator 800 compares the segment number and the page number of the 1st logic address with those of the 2nd logic address in parallel with the 2nd access. When the coincidence is obtained from said comparison, it is decided that both the 1st and 2nd logic addresses are included in the same page. Thus the 2nd access result is validated.
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