| 摘要 |
PURPOSE:To prevent a C-MOS semiconductor device from latching up by forming a second diffused region formed by superposing a first diffused region 22 on a well region 23 between the internal circuit of a chip at the center and input/output circuit of the periphery of the chip. CONSTITUTION:The P<+> type first diffused region 22 formed between an input/ output circuit and an internal circuit and a P<-> type well region 23 formed separated from the region 22 are superposed to form the P<+> type second diffused region 24. The regions 22, 24 are formed simultaneously with the source and drain regions 2, 3, 13, 14 of P-channel MOS transistors 5, 16. The regions 22, 24 are formed in ring shape to surround the entirety of the internal circuit to form a parasitic PNP transistor. A parasitic transistor Tr 4 is conducted by this structure, and even if a voltage of 0.6V is generated across a resistor R4, the voltage is divided by series resistance of a resistor R1 and a resistor R3, and the voltage generated across the resistor R1 becomes 0.6V or lower. As a result, the transistor Tr 1 is not conducted to eliminated a latchup.
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