| 摘要 |
PURPOSE:To reduce a process time by providing a shift register that outputs a serial data in series and in parallel, and enabling the inversion and outputting of the polarity of each bit of data in the latter half portion of the shift register when the specified bit arrangement of the parallel data from the first half portion of the shift register is detected. CONSTITUTION:A shift register 21 in a reception circuit 2 is divided into two portions, the first half portion 21a and the latter half portion 21b, and a serial data from the portion 21b is taken out through an inverting means 22 and an output from a detecting means 23 that makes input the parallel data from the portion 21a is supplied to each set terminal of a counter 24 and an FF25. Furthermore, the output of the counter 24 is supplied to the reset terminal of the FF25, and the output is inputted to the means 22, and when the specified bit arrangement of the parallel output of the portion 21a is detected by the means 23, it is informed to the counter 24 and the FF25, and the serial data output of the register 21 in the setting time of the FF25 is inverted by the means 22. |
