| 摘要 |
PURPOSE:To obtain the title circuit not applying external switching control to an MOSFET level and a TTL level by providing the 1st latch circuit reading an output signal of an input buffer to the gate electrode of which an external signal is given during the low level '0' of a clock signal and the 2nd latch circuit reading the said output signal during '1' period. CONSTITUTION:The size of N channel MOS transistors (TRs) 12, 13 is selected so that a MOSFET level is detected when the N-channel MOS TR 12 is turned on and the N-channel MOS TR 13 is turned off and a high level '1' of the TTL level is detected when both the N-channel MOS TRs 12 and 13 are turned on. A latch circuit 16 inputs an output of an inverter 15 and uses an output of the inverter 14 as a clock signal. A flip-flop circuit 17 is set by an automatic clear signal ACL and reset by an output signal B of the latch circuit 16. A latch circuit 19 is a circuit inputting the output signal of the inverter 15 and reading it by using a clock signal phi.
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