| 摘要 |
Digital timing unit for timing data processing systems or units thereof, wherein the output signals of a shift register are applied to a plurality of EXCLUSIVE OR gates (G1) .... (Gn).
<??>The shift register, at first in a known status, is activated so that an electrical transition is shifted through the register cells and defines a timing cycle, at the end of which the register is set in a second known status.
<??>A feedback and control logic (3, 4, 5, 6, 7, 8, 9) allows to activate the register independently from its status and to keep it in the status occuring at the end of a timing cycle until a new start signal is received.
<??>The shift of the register is caused by timing pulses generated by an oscillator (1).
<??>The timing signals generated by the timing unit and present on the outputs of the EXCLUSIVE OR may be modified, as to the length, by changing the oscillator period and/or the connection between the EXCLUSIVE OR inputs and the outputs of the shift register. |
