| 摘要 |
<p>PURPOSE:To eliminate the processing time except the time required substantially for synchronous locking and to decrease the restoring time from the locking time and out of synchronism by providing the number of consecutive coincidence count means in response to the bit number for a large frame and a synchronization check means. CONSTITUTION:A frame synchronizing circuit consists of a bit synchronizing circuit 1, a timing pulse generator 14, consecutive coincidence counter circuits 20, 30, 40, synchronizing check circuits 60, 70, 80 and an OR circuit 15. For example, the circuit 20 consists of an AND circuit 21, coincidence detection circuits 22A, 22B, 22C (hereinafter A, B, C are omitted), a dissidence detection circuit 23, a counter 24, and a synchronizing pattern generating circuit 25. Thus, the synchronizing bit is detected by applying consecutive coincidence count for a large frame's share. That is, in case of a 3-bit synchronizing pattern, three kinds of synchronizing patterns subject to phase shift and a received code series are subject to consecutive coincidence count at the same time. Thus, even when the synchronizing patterns are received in any order, the synchronizing bit is extracted by using the consecutive coincidence countmeans 20, 30, 40 for a large frame's share to generate a frame trigger pulse.</p> |
