Full adder circuit with sum and carry selection functions.

摘要

A logic operation circuit includes an exclusive-OR circuit (10) for receiving first and second input signals, a sum signal selection circuit (12) for selectively generating a carry output signal or an inverted signal thereof as a carry output signal in accordance with an output signal from the exclusive-OR circuit (10), and a carry output signal selection circuit (14) for selectively generating the carry input signal or the first input signal as a sum signal in accordance with the output signal from the exclusive-OR circuit (10). The exclusive-OR circuit (10) includes a double balance type differential amplifier connected between first and second power source terminals, and the sum signal selection circuit (12) includes a double balance differential amplifier operated in accordance with the output signal from the exclusive-OR circuit (101 and the carry input signal and connected between the first and second power source terminals.