| 摘要 |
A high speed programmable prescaler has an input divider that divides an input stream of clock pulses by either 2 or upon command by 3. Connected to the input divider is a plurality of dividers that are electrically cascaded together from a first member to last member with each member of the plurality of dividers being capable of dividing the clock pulses applied to it by either 2 or upon command by 3. A prescaler selects either 2 or 3 for dividing the input stream of clock pulses so that number of clock pulses necessary to obtain an output pulse can be represented by the equation of 2N+M where N is the number of members of the plurality of dividers and M is the control number having a range of 0 to 2N-1. The critical path delays are minimized by using a flip-flop in the input divider to divide by 2 and then on command shifting the output of the flip-flop by 180 DEG to obtain the divide by 3 function.
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