发明名称 VITERBI DECODING CIRCUIT
摘要 PURPOSE:To decode transmission data for one burst's share in one frame correctly as one burst's share even at the decoding side by providing a simple editing function to the circuit. CONSTITUTION:An ACS (addition, comparison, selection) circuit 22 inputs a path metric outputted from a branch metric generating circuit 21 and a path metric storage circuit 23 and applies addition, comparison and selecting operation to it. An edition circuit 25 rearranges decoded data based on the decoding data outputted from a survival path storage circuit 24 and a burst control signal from an input terminal 12 and outputs arranged decoding data from an output terminal 13. In the first half read from an address (d+1) to an address (r), the k-th frame decoding data is read and the decoding data of the (k+1)-th frame leading to the preceding frame fetched newly is read via the write to a storage circuit in the latter half read from the address 1 to an address (d) succeedingly, and the decoding data separated over the 2 frames is arranged as one burst's share of the transmission data correctly.
申请公布号 JPS60183823(A) 申请公布日期 1985.09.19
申请号 JP19840039865 申请日期 1984.03.02
申请人 NIPPON DENSHIN DENWA KOSHA;TOSHIBA KK 发明人 ATSUGI GAKUO;TAJIMA MASATO;SUZUKI HIDEO;TAKAHASHI KIYOAKI;TAKENAKA NOBUO
分类号 H03M13/23 主分类号 H03M13/23
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