| 摘要 |
PURPOSE:To test simultaneously a memory cell part in a compartment by switching an operation mode to a test mode by a flip-flop and an OR gate group. CONSTITUTION:A normal operation mode sets a flip-flop 2 to a state ''0'' and designates it. Accordingly, in case of a write operation, one of output signal lines 10-13 from a compartment selecting circuit 1 becomes a state ''1'', therefore, only one signal line of the output signal lines 30-33 from an OR gate group 3 becomes ''1'', and data is written in an address designated by an address signal line 4. In case of a read-out operation, the data is read out of a buffer memory designated by the address signal line 4. The test mode sets the flip- flop 2 to a state ''1'' and designates it. Accordingly, in case of a write operation, the state ''1'' is inputted to a write approval terminal of all buffer memories, and the data is written simultaneously in the address designated by the address signal line 4. In case of a read-out operation, a data on a buffer memory address designated by the address signal line 4 is read out simultaneously, and the state ''1'' is inputted to all output inhibiting terminals S of buffer selecting circuits 70-73. |
