| 摘要 |
PURPOSE:To improve the processing speed by executing a correcting phase in the same cycle as the phase of intermediate sum for the addition being the 2nd and succeeding, in executing the accumulative addition of plural binary coded decimal numbers by means of 3-input binary adders. CONSTITUTION:In executing the accumulative addition of n-set of decimal numbers Di, values D1, D2 are set respectively to registers 2, 3, intermediate sums S0-S3 outputted from the adder 1 are set to the register 2 in the 1st addition phase, carry outputs C0-C3 of each digit are set to a holding register 5 and the next value D3 is set to the register 3. The intermediate sum of the (i-1)th addition from the register 2 in the i-th adder is applied to the 1st input of the register 3, a value Di+1 is applied to the 2nd input from the register 3, (0) is applied to a CIN input, and (0) or (6) is selected at each digit depending on the content of the register 5 and applied to the 3rd input. In the final correcting phase, 0000 is applied to the 2nd input from the register 3, (1) is applied to the CIN input and the selecting circuit 4 selects (9) or F and applies it to the 3rd input. |
