发明名称 MULTIPLEX INTERFACE CIRCUIT CONNECTING A PROCESSOR TO A SYNCHRONOUS TRANSMISSION MEANS
摘要 Message interchange system among microprocessors connected by a synchronous transmitting means (1, 2), in which a microprocessor (PU), in order to send a message to another microprocessor, transfers the message words, as well as a state word, to a conventional read-and-write memory unit (ME), then it sends a signal enabling the operations and a signal enabling the reading in said memory unit (ME) to a first logic circuit (LC) that continues to autonomously transfer said messages from said memory unit (ME) to said transmitting means (1, 2) and in which a microprocessor in order to receive a message from another microprocessor sends to said first logic circuit (LC) a signal enabling the operation and a signal enabling the reading in said memory unit (ME), said logic uit (LC) receiving also an acknowledgement signal of a start message word.
申请公布号 DE3066348(D1) 申请公布日期 1984.03.08
申请号 DE19803066348 申请日期 1980.04.17
申请人 CSELT CENTRO STUDI E LABORATORI TELECOMUNICAZIONI S.P.A. 发明人 GANDINI, MARCO;VIALE, ERNESTO
分类号 G06F13/00;G06F15/16;G06F15/167;G06F15/177;H04L13/18;H04L25/05;H04Q11/04;(IPC1-7):G06F15/16;H04L25/38;H04Q3/54 主分类号 G06F13/00
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