| 摘要 |
PCT No. PCT/JP79/00235 Sec. 371 Date Jun. 3, 1980 Sec. 102(e) Date Jun. 3, 1980 PCT Filed Sep. 4, 1979 PCT Pub. No. WO80/00761 PCT Pub. Date Apr. 17, 1980.A semiconductor memory device is provided which includes a first transistor (TR1) having its emitter grounded, a second transistor (TR2) having its base and collector connected to the collector and base of the first transistor (TR1) and its emitter grounded, a data line (DL), and a third transistor (TR5) having its emitter-to-collector path connected between the data line (DL) and the base of the second transistor (TR2). The semiconductor memory device further includes a fourth transistor (TR6) having its base connected to another collector of the second transistor (TR2) and a fifth transistor (TR7) having its emitter-to-collector path connected between the base of the fourth transistor (TR6) and the row select line. Data is written through the data line (DL) and third transistor (TR5) and stored data is read out of the collector of the fourth transistor according to the conduction state of the second transistor (TR2).
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