发明名称 COMPUTER SYSTEM
摘要 PURPOSE:To reduce the hardware and the entire processing time, by directly transmitting and receiving required instructions and data between an external processor and a memory, in a system added with the external processor. CONSTITUTION:A processor 1 transmits a strobe signal to an external processor 3 at all times in synchronizing with the timing of instruction fetch and execution cycle. On the other hand, the external processor 3 directly fetches read out instructions, number of operations and number to be operated in a memory bus from a memory 2, and required processing for the device 3 is made effective among them and unnecessary signals are made invalid. In storing the result of operation of the device 3 to the memory 2, the device 3 gives the result of operation directly on the memory bus 7 in synchronizing with the strobe signal and writes the result in the memory 2. Thus, the transmission and reception of the instructions and data can be made between the external processor 3 and the memory 2.
申请公布号 JPS57152045(A) 申请公布日期 1982.09.20
申请号 JP19810036030 申请日期 1981.03.13
申请人 HITACHI SEISAKUSHO KK 发明人 YAMAMOTO NOBORU;YONEMURA MASATOSHI;YUU KEIICHI
分类号 G06F7/00;G06F9/38;G06F15/16 主分类号 G06F7/00
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