| 摘要 |
<p>PURPOSE:To obtain a detailed log record, by providing a switching circuit on the input side of a signal holding circuit, also utilizing the delaying circuits which have been connected in series, delaying an input signal little by little in order, and holding it. CONSTITUTION:Gates G1-G8 and a gate G9 consist of a NOR circuit, and an inverter, respectively, and to each one input of the gates G3, G5 and G7 are connected delaying circuits D1-D3, respectively. Outputs of registers R1-R4 are supplied to a memory M. In this case, input signals WD1-WD4 are supplied to the gates G2, G4, G6 and G8, and an input signal WD0 is sent to the delaying circuits D1-D3. Said input signals WD0-WD4 are computer internal state signals, and when a switching signal SEL is ''0'', transient phenomena of the input signal WD0 are stored in order of time series of each register R1-R4.</p> |
