| 摘要 |
PURPOSE:To simplify the program of the master CPU, by designating addresses concerning data transfer by the slave CPU. CONSTITUTION:Master CPU20 disconnects address bus 30, data bus 40 and line 50 electrically from one another to output data transfer permission signal H to line 70 when slave CPU120 is permitted to access main storage device 10 after master CPU20 receives the data transfer request signal through line 60. When permission signal H is outputted, all input terminals of AND circuit 104 become high-level, and the high-level signal is outputted to line 105 to open gates of buffers 181, 182, and 183. Consequently, the address code is generated on address bus 30 through address busses 131 and 31, and data is generated on data bus 40 through busses 141 and 41, and the writing signal is generated on line 50 through lines 152 and 51, and thus, data is written in the address of main storage device 10. |
