| 摘要 |
<p>A clocked static memory comprising a memory matrix (10) including a plurality of static memory cells (11) arranged in rows and columns and providing a voltage differential at bit lines (13, 14) whenever an associated memory cell is selected. Sense amplifiers (22) are connected between the bit lines of each column and a sense clock line (27) connected to a sense driver (40) crosses transistors in a sense amplifier (22) in each column. A logic circuit (50) detects the actual data output on data lines (15, 16) coupled to the bit lines and is buffered by an amplifier (51) to provide a memory status output signal indicating the existence of valid data output. </p> |
