发明名称 DISTRIBUERAT PRIORITETSBESLUTSSYSTEM
摘要 Multiple stations exchange information without central supervision. Stations requiring a cycle of access time on a shared time-divided bus participate in a cyclic access resolution process. The station having highest priority for a next bus cycle indicates its precedence to the other stations, and assumes exclusive use of the bus in the next cycle. The bus may comprise separate sections for data and response communications. Separate access resolution processes are conducted relative to each section. After gaining access to the bus for one cycle of data transfer a station becomes ineligible to compete for access to the data section until it receives an associated response. Accordingly receiving stations may control both the rate of data transmittal and the rate of access competition activity at associated origin stations. The data and response communications may include address information for enabling stations to intercommunicate directly in pairs. Data processing stations subject to multi-level interruption may present control signals designating acceptable interruption priority levels. Other stations seeking to interrupt such processing stations are eligible to compete for access to the bus only if assigned interruption priorities are at designated levels.
申请公布号 SE7901517(L) 申请公布日期 1979.08.23
申请号 SE19790001517 申请日期 1979.02.21
申请人 IBM 发明人 DEVEER J A
分类号 G06F15/16;G06F13/00;G06F13/26;G06F13/368;G06F13/372;G06F13/374;G06F15/177;H04J3/16;H04J3/24;(IPC1-7):G06F3/04 主分类号 G06F15/16
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