| 摘要 |
In a system which includes a common bus to which a plurality of units are connected for the transfer of information, such as a data processing system, information may be transferred by the highest priority unit during an asynchronously generated bus transfer cycle. Logic is provided for enabling a first unit, such as a central processor, to make a multiple fetch request of a second unit, such as a memory, during a first transfer cycle. The multiple fetch request requests the second unit to transfer multiple parts of data to the first unit during multiple further transfer cycles, wherein one part of data is transferred in each further transfer cycle. Logic is provided in the second unit to enable the second unit to indicate to the first unit, except during the last further transfer cycle, that each further transfer cycle will be followed by another further transfer cycle. Logic is provided in the first unit to enable the first unit to accept less parts of data than originally requested in the multiple fetch request. This permits the first unit to make multiple fetch requests of other units on the bus without regard to whether the other units are capable of performing multiple fetch operations and eliminates the need for abnormal condition recovery logic in the second unit. Logic is also provided to permit the first unit to utilize each part of data as it is received by the first unit without requiring the first unit to wait for the last transfer cycle before using any of the received parts of data. |
