发明名称 |
SYSTEM CLOCK SPEED CONTROLLER |
摘要 |
2092172 9209028 PCTABS00013 In a portable computer the BIOS software slows the system clock frequency during idle periods. The BIOS software returns the system to its normal operating frequency when an awaited event such as a keystroke occurs. In the event of an interrupt while the system clock is at the lower frequency, a hardware clock control circuit responds to the interrupt to promptly increase the system clock frequency to the normal value. By decoding the old frequency, new frequency and the several available frequencies, the change in frequency is timed to maintain proper phase and duty cycle without interruption.
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申请公布号 |
CA2092172(A1) |
申请公布日期 |
1992.05.10 |
申请号 |
CA19912092172 |
申请日期 |
1991.09.24 |
申请人 |
WANG LABORATORIES, INC. |
发明人 |
BARRETT, DAVID M.;LETOURNEAU, MARY E.;MARTIN, PATRICIA A.;MCNALLY, J. MICHAEL |
分类号 |
G06F1/04;G06F1/08;G06F1/32;(IPC1-7):G06F1/08 |
主分类号 |
G06F1/04 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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