发明名称 A CONTROL SIGNAL INTERLOCKING SYSTEM
摘要 <p>An interlocking system comprising a plurality, e.g., three, of parallel sub-systems operating asynchronously to produce identical replicated outputs which are mutually compared to determine the correct output and disqualifying a minority output thereby ensuring high system integrity. Each sub-system includes a similar arrangement for computing the difference between all possible pairs of sub-systems. Comparison of these results with a reference table of all possible difference results and then comparison of the difference equations yields a common factor which is the sub-system producing the error. Action can then be taken to disqualify its output, e.g., by switching-off its power supply. A final output is taken, preferably from one sub-system, with a second as standby. To accomodate asynchronous running, a final output is only acted upon if it is repeated in a succeeding output cycle thus permitting opportunity to disqualify the preferred output if it is judged in error by the other sub-systems and to replace it by the standby.</p>
申请公布号 IN160140(B) 申请公布日期 1987.06.27
申请号 IN1982DE72319 申请日期 1982.09.24
申请人 WESTINGHOUSE BRAKE & SIGNAL COMPANY LIMITED 发明人 BROWN CHRISTOPHER ROBERT;CORRIE JOHN DOUGLAS;WILSON WILLIAM GEOFFREY JOHN
分类号 B61L27/00;G05B9/03;G06F11/16;(IPC1-7):B61L19/00;G06F15/00 主分类号 B61L27/00
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