发明名称 Processor resetting method and apparatus
摘要 In a communication network including a plurality of nodes, when it is desired for a processor A of one of the nodes to reset another processor B within the same node or within another of the nodes, the processor A side generates a reset cell and transmits it to the party processor B side through a channel. The party processor B side confirms that the received cell is a reset cell, accepts the cell, and outputs a reset signal to the processor B to reset the processor B.
申请公布号 US5581549(A) 申请公布日期 1996.12.03
申请号 US19930086888 申请日期 1993.07.07
申请人 HITACHI, LTD. 发明人 MOCHINAGA, TATSUO
分类号 G06F1/24;H04L12/56;H04L29/06;H04Q11/04;(IPC1-7):H04L12/56 主分类号 G06F1/24
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