Semiconductor memory device and method for adjusting internal voltage thereof

摘要

A semiconductor memory device improves test reliability by suppressing unnecessary leakage component in a USMC test which checks if data is normally transferred by extending a time margin between an active signal input time and a bit line sensing time. The semiconductor memory device includes at least one inner voltage adjusting unit for adjusting an inner voltage for limiting leakage portion that is generated in the semiconductor memory device during the USMC test by using a USMC signal for starting the USMC test and a termination signal for terminating the USMC test. The inner voltage adjusting unit includes a bulk bias voltage adjusting unit for supplying a bulk bias voltage to a cell transistor in the semiconductor memory device.