| 发明名称 | Data coherency model and protocol at cluster level | ||
| 摘要 | An apparatus for providing data coherency is described herein. The apparatus includes a global persistent memory. The global persistent memory is accessed using a protocol that includes input/output (I/O) semantics and memory semantics. The apparatus also includes a reflected memory region. The reflected memory region is a portion of the global persistent memory, and each node of a plurality of nodes maps the reflected memory region into a space that is not cacheable. Further, the apparatus includes a semaphore memory. The semaphore memory provides a hardware assist for enforced data coherency. | ||
| 申请公布号 | US9383932(B2) | 申请公布日期 | 2016.07.05 |
| 申请号 | US201314142733 | 申请日期 | 2013.12.27 |
| 申请人 | Intel Corporation | 发明人 | Das Sharma Debendra;Kumar Mohan J.;Fleischer Balint T. |
| 分类号 | G06F11/00;G06F3/06;G06F11/20;G06F13/32 | 主分类号 | G06F11/00 |
| 代理机构 | International IP Law Group, P.L.L.C. | 代理人 | International IP Law Group, P.L.L.C. |
| 主权项 | 1. An apparatus for providing data coherency, comprising: a global persistent memory, wherein the global persistent memory is accessed using a protocol that includes input/output (I/O) semantics and memory semantics; a reflected memory region, wherein the reflected memory region is a portion of the global persistent memory, and each node of a plurality of nodes maps the reflected memory region into a space that is not cacheable; and a semaphore memory, wherein the semaphore memory provides a hardware assist for enforced data coherency. | ||
| 地址 | Santa Clara CA US | ||