发明名称 SEMICONDUCTOR MEMORY
摘要 <p>PURPOSE:To input the next data before data is outputted to an output terminal and to read out data at high speed by detecting that the output of a sense amplifier is confirmed, and taking this output in a data latch circuit. CONSTITUTION:Delay from a cirtain address input up to confirmation of a sensor by a sense amplifier is detected by a sense confirmation detecting means 19. And a data latch circuit 16 is provided on the output side of an amplifier 15, time measurement for confirming a sense is performed by utilizing a dummy cell train incorporated in a memory cell array 11, sense output data is taken in the circuit 16, and the next address can be directly inputted before data is outputted from an output buffer 17. Also, address cycle margin is not required for an access time by holding sense output data in the circuit 16, and data access can be performed with shorter cycle than the access time. And a delay time until confirmation of the sense amplifier can be accurately measured, delay in an external capacitor and an output circuit is not caused, and high speed access can be performed.</p>
申请公布号 JPH0855492(A) 申请公布日期 1996.02.27
申请号 JP19940208009 申请日期 1994.08.09
申请人 YAMAHA CORP 发明人 SHICHIMIYA TAKATOMO
分类号 G11C17/00;G11C7/10;G11C8/18;G11C11/41;G11C16/06;G11C17/18;(IPC1-7):G11C17/18 主分类号 G11C17/00
代理机构 代理人
主权项
地址