Bus for data processing system with fault cycle operation.

摘要

A digital data processing system including a number of input/output units (12) that communicate with a memory (11) over an input/output bus (30) and through an input/output interface (31). The input/output interface (31) pipelines transfer between the input/output units (12) and the memory (11). In the event of an error in the input/output interface's pipeline buffer, it transmits information to the input/output (12) that initiated the transfer unit to enable it to re-initiate the transfer.