Time-slot assigner multiplexer.

摘要

For each channel, a pair of buffers permits "non-slip" transfer of data signals on and off a bus synchronized with signals on a time-division multiplexed pulse-code modulation (PCM) highway. A source buffer consisting of a serial-in, parallel-out register and two parallel-in, parallel-out registers receives signals from one of the PCM channels and transmits these signals onto a bus synchronized with a data-routing multiplexer employed within a digital exchange controller employing the device. A destination buffer consisting of two parallel-in, parallel-out registers and a parallel-in, serial-out register receives signal from the bus and, in conjunction with a transmit multiplexer, generates the signals on the PCM highway.