发明名称 Multiply-add unit and data processing apparatus using it
摘要 A multiply-add unit includes a digit alignment shift number and exponent generator unit, an addend digit alignment and sign adjusting unit, a multiplier array, a sticky-bit for addend lower digits generator unit, a leading digit detector unit, a carry propagate adder, an exponent normalizing unit, an addend higher digit incrementer, a sticky-bit generator unit, a normalizing shifter, a positive number conversion and rounder unit, and an exponent correction unit. The multiplier array is an array of carry save adders. The leading digit detector unit receives the two terms of carry and sum parts from the multiplier array, sequentially checks a digit pair of "0" to "1" at each corresponding digit position from the highest digit, and detects the leading non-zero digit of the absolute values depending upon what digit pair values are (11, 00, 10, 01) from higher to lower digit position.
申请公布号 US5889690(A) 申请公布日期 1999.03.30
申请号 US19980057397 申请日期 1998.04.09
申请人 HITACHI, LTD. 发明人 ARAKAWA, FUMIO
分类号 G06F7/544;(IPC1-7):G06F7/38;G06F7/00 主分类号 G06F7/544
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