Display drive circuit

摘要

Provided is a display drive circuit which is connected to a display panel including a gate drive circuit that scans gate electrodes, a source driver that drives source electrodes of the display panel, and a gate control driver that supplies a clock signal to the gate drive circuit. The display drive circuit performs an intermittent operation which is alternately provided with a display period in which the source electrodes are driven and an interruption period during which the display panel is not updated. During a start of the display period following the interruption period, the gate control driver extends a pulse width of the clock signal which is supplied to the gate drive circuit, or preliminarily outputs the clock signal before the start of the display period.

主权项

1. A display drive circuit connected to a display panel including a plurality of source electrodes, a plurality of gate electrodes, a plurality of display cells disposed at intersecting portions of the pluralities of source electrodes and gate electrodes, and a gate drive circuit that scans the plurality of gate electrodes, the display drive circuit comprising:
a source driver configured to drive the plurality of source electrodes; and a gate control driver configured to supply a clock signal to the gate drive circuit, wherein the source driver is configured to drive the plurality of source electrodes during a display drive period and stop updating the display panel using the plurality of source electrodes during an interruption period, wherein the display drive period and the interruption period are alternately performed, wherein the gate control driver is configured to output a gate pulse change period, wherein during the gate pulse change period a pulse width of the clock signal is extended during a start of the display drive period after the interruption period relative to the pulse width of the clock signal during a later portion of the display drive period, and wherein each of the plurality of display cells comprises a transfer gate transistor comprising a gate terminal connected to a corresponding gate electrode of the plurality of gate electrodes and a source terminal connected to a corresponding source electrode of the plurality of source electrodes.