发明名称 VERTICAL MEMORY DEVICES HAVING DUMMY CHANNEL REGIONS
摘要 A memory device includes a plurality of channel regions that each extend in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate adjacent the channel regions, each of the gate electrodes extending different lengths, and a plurality of dummy channel regions adjacent first ends of the plurality of gate electrode layers, wherein the substrate includes a substrate insulating layer formed below the plurality of dummy channel regions.
申请公布号 US2017040337(A1) 申请公布日期 2017.02.09
申请号 US201614987835 申请日期 2016.01.05
申请人 KIM Jong Won;LIM Seung Hyun;KANG Chang Seok;PARK Young Woo;BAE Dae Hoon;EUN Dong Seog;LEE Woo Sung;LEE Jae Duk;LIM Jae Woo;CHOI HanMei 发明人 KIM Jong Won;LIM Seung Hyun;KANG Chang Seok;PARK Young Woo;BAE Dae Hoon;EUN Dong Seog;LEE Woo Sung;LEE Jae Duk;LIM Jae Woo;CHOI HanMei
分类号 H01L27/115 主分类号 H01L27/115
代理机构 代理人
主权项 1. A semiconductor device, comprising: a semiconductor substrate; a gate electrode layer structure that includes a plurality of spaced-apart gate electrode layers stacked on an upper surface of the semiconductor substrate; a plurality of channel regions penetrating the gate electrode layers; a plurality of dummy channel regions penetrating at least the lowermost of the gate electrode layers; and a substrate insulating layer between the semiconductor substrate and the dummy channel regions.
地址 Hwaseong-si KR