发明名称 |
SEMICONDUCTOR ELEMENT, MANUFACTURING METHOD OF SEMICONDUCTOR ELEMENT, AND ELECTRONIC APPARATUS |
摘要 |
The present disclosure relates to a semiconductor element, a manufacturing method of a semiconductor element, and an electronic apparatus, which enable suppression of crack occurrences and leaks.;The present technology has a laminated structure including an insulating film having a CTE value between those of metal and Si and disposed under a metal wiring, and P—SiO (1 μm) having good coverage and disposed as a via inner insulating film in a TSV side wall portion. As the insulating film having a CTE that is in the middle between those of metal and Si, for example, SiOC is used with a thickness of 0.1 μm and 2 μm respectively in the via inner insulating film and a field top insulating film continuous to the via inner insulating film. The present disclosure can be applied to, for example, a solid-state imaging element used in an imaging device. |
申请公布号 |
US2017005128(A1) |
申请公布日期 |
2017.01.05 |
申请号 |
US201415101075 |
申请日期 |
2014.12.05 |
申请人 |
SONY CORPORATION |
发明人 |
SASAKI Naoto |
分类号 |
H01L27/146;H01L23/528;H01L23/532;H04N5/378;H01L21/768;H04N5/365;H04N5/3745;H04N5/376;H01L23/48;H01L23/31 |
主分类号 |
H01L27/146 |
代理机构 |
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代理人 |
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主权项 |
1. A semiconductor element, comprising:
a through silicon via (TSV) formed in a substrate; a side wall film formed in a side wall portion of the TSV and having good coverage; and an insulating film formed in a layer under a metal wiring except for a via portion of the TSV, wherein the insulating film is of a film type in which a coefficient of thermal expansion has a value between a coefficient of thermal expansion for the substrate and a coefficient of thermal expansion for the metal wiring. |
地址 |
Tokyo JP |