发明名称 半導体装置
摘要 PROBLEM TO BE SOLVED: To provide a semiconductor device capable of reducing voltage dependency of a capacitance formed with a wiring pattern, with no increase in parasitic capacitance.SOLUTION: In a semiconductor device, a pair of metal wiring patterns which extends in the first direction and forms an electrode of a capacitive element is formed in a wiring layer above a semiconductor substrate, and on a well formed at the semiconductor substrate, a polysilicon film which is an electrically floating dummy pattern is formed through an insulator film. A p-type well and an n-type well, above which the polysilicon film which is a dummy pattern is formed, are arranged below the metal wiring pattern, so that a voltage dependency of parasitic capacitance related to a p-type well region and that related to an n-type well region are offset, thereby reducing voltage dependency of a capacitance formed by the wiring pattern.
申请公布号 JP5942471(B2) 申请公布日期 2016.06.29
申请号 JP20120040013 申请日期 2012.02.27
申请人 株式会社ソシオネクスト 发明人 山▲崎▼ 修;久光 一也;古川 幸泰;荒木 崇;坂倉 宏
分类号 H01L21/822;H01L21/3205;H01L21/768;H01L23/522;H01L27/04 主分类号 H01L21/822
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