| 发明名称 |
METHOD OF GENERATING TECHFILE HAVING REDUCED CORNER VARIATION VALUE |
| 摘要 |
A method of generating a techfile corresponding to a predetermined fabrication process is disclosed. The method includes determining a typical value and a corner variation value usable to model an electrical characteristic of a layer of back end of line (BEOL) features to be fabricated by the predetermined fabrication process, based on measurement of one or more sample integrated circuit chips fabricated by the predetermined fabrication process. A reduced variation value is calculated based on the corner variation value and a scaling factor. The techfile is generated based on the typical value and the reduced variation value. |
| 申请公布号 |
US2016034631(A1) |
申请公布日期 |
2016.02.04 |
| 申请号 |
US201414446752 |
申请日期 |
2014.07.30 |
| 申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. |
发明人 |
WANG Chung-Hsing;TAM King-Ho;CHEN Yen-Pin;CHEN Wen-Hao;LIN Chung-Kai;YAO Chih-Hsiang |
| 分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A method of generating a techfile corresponding to a predetermined fabrication process, the method comprising:
determining a typical value and a corner variation value usable to model an electrical characteristic of a layer of back end of line (BEOL) features to be fabricated by the predetermined fabrication process, based on measurement of one or more sample integrated circuit chips fabricated by the predetermined fabrication process; calculating a reduced variation value based on the corner variation value and a scaling factor; and generating the techfile based on the typical value and the reduced variation value. |
| 地址 |
Hsinchu TW |
