发明名称 WAFER PACKAGING STRUCTURE AND PACKAGING METHOD
摘要 The present invention provides a wafer packaging structure and a wafer packaging method. The wafer packaging structure includes: a substrate, wherein grooves are formed in one surface of the substrate, and chips are arranged in the grooves; a material sealing layer formed on the substrate, wherein connecting components of the chips are exposed from the surface of the material sealing layer; a wiring layer formed on the material sealing layer and electrically connected with the connecting components; a protective film layer formed on the wiring layer, wherein the protective film layer is provided with openings for exposing the wiring layer; lower ball metal layers formed in the openings and connected with the wiring layer; and metal balls formed on the lower ball metal layers. The wafer packaging structure provided by the present invention can be used for packaging a plurality of chips, thereby having a higher integration level and a higher integration degree.
申请公布号 US2015380369(A1) 申请公布日期 2015.12.31
申请号 US201414764151 申请日期 2014.09.26
申请人 NANTONG FUJITSU MICROELECTRONICS CO., LTD 发明人 DING Wanchun
分类号 H01L23/00;H01L25/065;H01L23/29;H01L25/00;H01L23/31;H01L23/544 主分类号 H01L23/00
代理机构 代理人
主权项 1. A wafer packaging structure, comprising: a substrate, wherein grooves are formed in one surface of the substrate, and chips are arranged in the groove; a material sealing layer formed on the substrate, wherein connecting components of the chips are exposed from the surface of the material sealing layer; a wiring layer formed on the material sealing layer and electrically connected with the connecting components; a protective film layer formed on the wiring layer, wherein the protective film layer is provided with openings for exposing the wiring layer; lower ball metal layers formed in the openings and connected with the wiring layer; and metal balls formed on the lower ball metal layers.
地址 Nantong, Jiangsu CN
您可能感兴趣的专利