发明名称 INTEGRATED CIRCUIT DEVICE
摘要 PROBLEM TO BE SOLVED: To collectively apply ECC (Error Checking and Correcting) processing to a large number of memory macros while suppressing increase of an area in an integrated circuit device mounted with an ECC function. SOLUTION: For example, this integrated circuit device is provided with partial ECC code generation circuits 313 respectively correspondingly to the plurality of memory macros 311 each having memory capacity of 16 kb. Each the partial ECC code generation circuit 313 codes holding data of an address n of the corresponding memory macro 311 according to a rule of a partial Hamming code determinant by a NOP (No Operation)interrupt to the memory macro 311 in a suspension state. By transferring a partial ECC code coded by each the partial ECC code generation circuit 313 through a signal line SL and an adder 319, 10-bit ECC code data corresponding to the whole holding data are generated and stored in the address n of a code storage memory 321. COPYRIGHT: (C)2008,JPO&INPIT
申请公布号 JP2008090419(A) 申请公布日期 2008.04.17
申请号 JP20060268072 申请日期 2006.09.29
申请人 TOSHIBA CORP 发明人 KUSHIDA KEIICHI
分类号 G06F12/16;G06F11/10 主分类号 G06F12/16
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