发明名称 |
METHOD FOR GENERATING CLOCK FOR SYSTEM OPERATING AT RISING EDGE |
摘要 |
A method of converting an input clock to generate an output clock and providing a certain system with the output clock is provided. The method includes setting up a desired output clock value and a variable value and determining whether the input clock is the rising edge; adding the output clock value to the variable value to provide a calculated value when the input clock is the rising edge; comparing the calculated value with the input clock value; and outputting, when the calculated value is equal to or larger than the input clock value as a result of comparison, the output clock as logic state ‘1’ and setting, a value obtained by subtracting the input clock value from the calculated value, as the variable value. |
申请公布号 |
US2015214941(A1) |
申请公布日期 |
2015.07.30 |
申请号 |
US201414524508 |
申请日期 |
2014.10.27 |
申请人 |
LSIS CO., LTD. |
发明人 |
LEE Ji Geon |
分类号 |
H03K5/1534 |
主分类号 |
H03K5/1534 |
代理机构 |
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代理人 |
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主权项 |
1. A method of generating a clock for a system operating at a rising edge, converting an input clock to generate an output clock and providing a certain system with the output clock, the method comprising:
setting up a desired output clock value and a variable value and determining whether the input clock is the rising edge; adding the output clock value to the variable value to provide a calculated value when the input clock is the rising edge; comparing the calculated value with the input clock value; and outputting, when the calculated value is equal to or larger than the input clock value as a result of comparison, the output clock as logic state ‘1’ and setting, a value obtained by subtracting the input clock value from the calculated value, as the variable value. |
地址 |
Anyang-si KR |