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摘要

PROBLEM TO BE SOLVED: To reduce capacitance between a gate and a source, and between a gate and a drain, and prevent a gate for applying a voltage required for turning on a JFET (junction field effect transistor) from becoming high.

SOLUTION: A p+type gate region 4 is directly formed on the surface of an n-type channel layer 2 so that a part away from the n-type channel layer 2 becomes wide compared to a part contacting the n-type channel layer 2 out of the p+type gate region 4. The wide part of the p+type gate region 4 is made to be separated from the n-type channel layer 2 by a predetermined distance. For example, a recess 2a is formed on the n-type channel layer 2, and the p+type gate region 4 is formed in the recess 2a.

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