| 发明名称 |
MULTIPLEXER FLOP |
| 摘要 |
In an embodiment, a flip flop circuit includes a master latch and a slave latch. The master latch comprises a storage element, a first data leg, and a second data leg. The first and second data legs may be coupled to the storage element. Clock selection logic may be coupled to the first and second data legs. The clock selection logic may have a select input for selecting between the first and second data legs. The slave latch may be coupled to the master latch. |
| 申请公布号 |
US2015061741(A1) |
申请公布日期 |
2015.03.05 |
| 申请号 |
US201414217935 |
申请日期 |
2014.03.18 |
| 申请人 |
CAVIUM, INC. |
发明人 |
Balasubramanian Suresh;Mohan Nitin;Salvi Manan |
| 分类号 |
H03K3/037 |
主分类号 |
H03K3/037 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A flip flop circuit comprising:
a master latch comprising a storage element, a first data leg, and a second data leg, the first and second data legs coupled to the storage element, and clock selection logic coupled to the first and second data legs, the clock selection logic having a select input for selecting between the first and second data legs; and a slave latch coupled to the master latch. |
| 地址 |
San Jose CA US |
