Quasi-digital receiver for high speed SER-DES

摘要

Techniques are described herein that provide an interface for receiving and deserializing digital bit stream(s). For instance, a receiver for a high-speed deserializer may include digital slicers, a digital phase interpolator, and a digital clock phase generator. The digital slicers may be configured to determine a digital value of a data input. The digital phase interpolator may be configured to generate an interpolated clock signal based on input clock signals that correspond to respective phases of a reference clock. The phase of the interpolated clock tracks the data input to the receiver through a clock recovery loop. The digital clock phase generator may be configured to generate output clock signals to control timing of the respective digital slicers. The receiver may further include a single digital eye monitor configured to monitor a data eye of the data input.

主权项

1. A receiver for a high-speed deserializer comprising:
a plurality of digital slicers configured to determine a digital value of a data input; a digital phase interpolator configured to generate an interpolated clock signal based on a plurality of input clock signals that correspond to a plurality of respective phases of a reference clock in order to track a phase of the data input to the receiver through a clock recovery loop; and a digital clock phase generator that receives the interpolated clock signal and is configured to generate a plurality of output clock signals received by the plurality of digital slicers to control timing of the plurality of digital slicers, the plurality of output clock signals based on a plurality of respective phases of the interpolated clock signal.