| 摘要 |
A memory unit (500) for handling data memory references of a multi-threaded processor provided with interleaved inter-thread pipeline in emulated shared memory (ESM) architectures, comprising a step cache (504) defining associative cache memory array in which data stays valid till the end of ongoing step of multithreaded execution, said memory array incorporating a plurality of cache lines with data fields, each line, preferably exclusively, containing a data field for address tag and a data field thread id of the first thread referring to a data memory location specified by the address tag, a scratchpad (506) defining a memory buffer for storing internal data of multioperations, such as intermediate results, said buffer including, preferably exclusively, a single data field for each thread of the processor, wherein the memory unit is configured to access the step cache for a cache search and scratchpad for retrieving and/or storing said internal data at different clock cycles and different stages of the processor pipeline during multioperation execution involving data memory (508) reference by the processor. A corresponding method for handling memory references is also presented. |
