Latch isolation circuit

摘要

A system and method have been provided for passively isolating a latch circuit. The method provides a latch having a first input, an output, and a reset port. The latch first input is selectively connected to a first reference voltage. While the latch first input is connected to the first reference voltage, the latch is reset. Subsequent to disconnecting the latch first input from the first reference voltage, a first node is selectively connecting to the latch first input. In response to selectively connecting the first node, a first analog signal is supplied to the latch first input. Subsequent to resetting the latch, the first analog signal is captured and the latch output supplies a digital signal responsive to the captured first analog signal.

主权项

1. A latch isolation circuit comprising:
a first node (CP) to supply a first analog signal; a latch having a first input (LP) to receive the first analog signal, an output to supply a digital signal responsive to the first analog signal, and a reset port, wherein the latch resets in response to a first edge of a periodic first clock (PH1) and captures the first analog signal on a second edge of PH1; a reset switch configured to selectively connect the latch first input to a first reference voltage in response to a periodic reset pulse (RST); a first series switch configured to selectively connect the first node (CP) to the latch first input (LP) in response to a periodic second clock (PH2); wherein the first edge of the PH1 occurs subsequent to a first edge of RST, but prior to a second edge of RST; and a first edge of PH2 occurs subsequent to the first edge of PH1 and a second edge of PH2 occurs subsequent to the second edge of PH1.