发明名称 CRITICAL SIZE COMPENSATING METHOD OF DEEP GROOVE ETCHING PROCESS
摘要 Disclosed is a critical size compensating method of a deep groove etching process. The method comprises: a difference of etching critical size is got; and an etching masking layer layout of a wafer is compensated according to a distance of an etching position and a center position of the wafer and the difference of etching critical size; deep groove etching is conducted to the wafer according to the compensated masking layer layout. By the adoption that an etching pattern size of the masking layer layout is compensated with a half of the difference of critical size as a compensation value, the etching speed and the etching size differences due to the fact that critical sizes of different positions of the wafer in the deep groove etching process distribute unevenly are improved, so that the uniformity of the critical sizes of a deep groove etching structure is improved greatly.
申请公布号 WO2014108036(A1) 申请公布日期 2014.07.17
申请号 WO2013CN91145 申请日期 2013.12.31
申请人 CSMC TECHNOLOGIES FAB1 CO., LTD. 发明人 ZHANG, ANNA;LI, XIAOMING
分类号 H01L21/66;H01L21/02 主分类号 H01L21/66
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